1. Field of the Invention
The present invention relates to integrated circuit memory, and particularly it relates to green transistor serving as select transistor for nano-Si ferro-electric RAM and method of operating the same.
2. Description of Prior Art
FeRAM (Ferro-electric RAM) is a nonvolatile memory which utilizes the ferro-electric effect of ferro-electric material to realize data storage. The ferro-electric effect occurs when a strong external electric field is applied to a ferro-electric material, the ions in the ferro-electric crystal may be displaced from its position so that the positive and negative charge centers do not coincide with each other, i.e. a polarization is formed in the material. Furthermore, when the external electric field is removed, the polarization still remains. Therefore, the ferro-electric effect has been proposed to be used as non-volatile memory (referred to as ferro-electric memory or FeRAM) with attractive features of small cell size, low-voltage operation, and fast program/erase. However, the manufacturing process for FeRAM is not compatible with CMOS process, e.g. the conventional ferro-electric materials (e.g. PZT, BST) are easily degraded by hydrogen annealing in CMOS flow and leads to poor memory retention. Therefore, there is a need for new ferro-electric material which is compatible with the CMOS process for the development of FeRAM.
Recently, the “nano-Si in porous SiO2” demonstrates its ferro-electric effect and fabrication method highly compatible with CMOS process. FIG. 14 illustrates the structure of nano-Si in porous SiO2, which includes nano-Si particles 2 within those nano-size pores or cavities of the porous SiO2 1. Normally, the nano-Si particles 2 within nano-size pores are randomly embedded in the porous SiO2 1. When an external electric field is applied to the material of “nano-Si in porous SiO2”, the chemical bonds between Si atoms of the nano-Si particles 2 and the oxygen atoms on the inner surface of pores may be distorted toward the direction of the electric field. As a result, these distorted bonds collectively result in average charge separation in the material and therefore polarization is formed and remains there even after the electric field is removed. Therefore, the “nano-Si in porous SiO2” can serve as the ferro-electric material for FeRAM applications. Furthermore, the material and fabrication of nano-Si in porous SiO2 is highly compatible with CMOS process, which can easily replace the PZT based ferro-electric material in FeRAM.
Similar to other nonvolatile memories, a FeRAM contains a plurality of memory cells which forms a memory array. U.S. Pat. No. 6,163,482 proposed a new FeRAM cell using a MOSFET transistor with spacer of ferro-electric material (e.g. PZT or BST) as data storage element. FIG. 15 is a schematic view of such a memory cell with n-channel MOSFET, including a substrate 100, a gate 101 on the substrate 100, a source 102 and a drain 103 inside the substrate 100 and on both sides of the gate 101, a second implant region 104 inside the drain 103 and near the gate 101, the second implant region 104 has the opposite doping type than the source 102 and the drain 103, and a spacer 105 of ferro-electric material is on the gate 101 and near the drain 103.
In the above FeRAM, the MOSFET serves as a select transistor of the memory cell, and the spacer 105 as the data storage element of the memory cell. FIG. 16 illustrates the equivalent circuit of the above FeRAM cell including the MOSFET and the diode inside the drain. An n-type MOSFET in the FeRAM cell is assumed to illustrate the read and write operations in the following text.
During a write operation, the source 102 and drain 103 is left floating, an external electric field across the spacer 105 is established by applying a voltage at the gate 101 and another voltage at the second implant region 104. Under this external electric field with large enough field intensity, the spacer 105 of ferro-electric material can be polarized with the polarization direction (defined as that pointing from the induced negative charge to the induced positive charge inside the spacer 105) the same as the external electric field. Therefore, the polarization in the spacer 105 can be altered with either direction simply by applying a large enough voltage bias with proper polarity across the gate 101 and the second implant region 104. The digital data “1” or “0” can be represented arbitrarily by the direction of the polarization in the spacer 105 corresponding to the bias polarity from the second implant region 104 to the gate 101 or in reverse manner during write operation respectively.
During a read operation, the second implant region 104 is left floating; the gate voltage is higher than the threshold voltage (Vt) of the MOSFET to turn on the MOSFET. Since a polarization in the spacer 105 will induce charge near the channel and affects the magnitude of the turn-on current depending on the direction of polarization. For example, when the polarization in the spacer 105 is from the second implant region 104 to the gate 101, the induced negative charge in the spacer 105 near the drain 103 repels electrons in the channel and lead to low channel current in the NMOS. If the direction of polarization is reversed, the induced positive charge in the spacer 105 near the drain 103 will result in larger channel current. Therefore, the direction of polarization in the spacer 105 (representing the data “1” or “0”) can be determined by the magnitude of the channel current. In the above FeRAM, the digital data “1” or “0” is arbitrarily defined corresponding to the low and high channel current respectively.
The future low-power trend needs a device technology that can be operated at low Vdd.
The concept of green MOSFET (referred to as green transistor or gFET) offers one solution for low Vdd operation of transistors, which has been reported by C. Hu et al. in the paper titled ‘Green Transistor—A VDD Scaling Path for Future Low Power ICs on 2008, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)’. The gFET enhances the band-to-band tunneling (BTBT) and results in large gate-induced-drain-leakage (GIDL) current by implanting the opposite type of dopant into the source or drain. The band-to-band tunneling is a mechanism that electrons move between the valence band and conduction band by tunneling without getting over the energy barrier, thus the gFET can achieve sharper I-V curves between the on and off states better than the well-known limit of 60 mv/decade of the conventional MOSFET.
FIG. 17a illustrates a conventional gFET, including a silicon-on-insulator (SOI) 10, which includes a substrate 11, a buried oxide 12 and a top silicon 13; a gate oxide 16 on the top silicon 13; a gate 17 on the gate oxide; and a source 14 and a drain 15 with different conductivities are formed separately on two sides of the gate oxide 16 and in the top silicon 13. The gFET also includes a neighboring lightly-doped region 19 and a pocket implant region 18 in the top silicon 13, which are separately aligned to each side of the gate oxide 16. Both of the pocket implant region 18 and the lightly-doped region 19 have the same conductivity with the drain 15. And the source 14, the drain 15 and the lightly-doped region 19 all contact with the buried oxide 12, the pocket implant region 18 of less depth does not contact with the buried oxide 12.
For convenience, the type of gFET is defined as the type of the pocket implant region 18, for example, a p-type gFET includes a p-type pocket implant region 18, an n-type source 14, and a p-type drain 15 correspondently. It should be noted that the carriers for conduction in gFET include both electrons and holes. Therefore, among the two terminals of the gFET, the implant region near the pocket implant region 18 is defined as the source 14, and the other implant region is defined as the drain 15. The material of the gate 17 is compatible with the CMOS process, which is metal or doped poly-silicon. A further description of the p-type gFET is in the following.
Referring to FIG. 17b, the band diagram of band-bending near the pocket implant region 18 of the p-type gFET is illustrated with gFET on (solid curves) and off (dotted curves). When the gFET is off (with the gate 17 biased at 0 v or more positive than the source 14), the lower edge of the conduction band (Ec) of the implant region 18 is higher than the upper edge of the valence band (Ev), which leads to a large barrier and no electrons transferring between the conduction band and the valence band. However, when the gFET is on (with the gate 17 biased to negative enough than the source 14), the voltage of the implant region 18 is lowered (or higher potential energy as the solid and diagram curves). Therefore, the upper edge of valence band of the implant region 18 is higher than the lower edge of the conduction band. Under this condition, electrons in the valence band can tunnel into the conduction band, with holes generated in the valence band correspondently.
FIG. 17c illustrates the currents when the p-type gFET is on. Referring to FIG. 17b and FIG. 17c, when the source 14 is biased to a voltage higher than the drain 15 (Vsd>0), and the gate 17 is biased negatively enough than the source 14, the valence band electrons in p-type pocket implant region 18 can tunnel into the conduction band of the n-type source 14. The holes in p-type pocket implant region 18 move toward p-type drain 15 through the lightly-doped region 19 simultaneously. As a result, a current is produced from the source 314 to the drain 315, which shows the gFET is on.
The conduction carriers are both electrons and holes in the gFET after turn-on; this is obviously different from the conduction in conventional MOSFET by majority carriers. The gFET has many advantages than the conventional MOSFET, including smaller sub-threshold swing (smaller than the 60 mV/decade limit in conventional MOSFET), lower turn-on voltage (lower than ˜0.2V) of gFET, less power consumption and high driving current. We intend to use the gFET with ferro-electric spacer as the FeRAM cell in this invention.